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2010-2012 Microchip Technology Inc.
DS41412F-page 49
PIC18(L)F2X/4XK22
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the pri-
mary clock occurs (see Figure 3-3). When the clock
switch is complete, the HFIOFS or MFIOFS bit is
cleared, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The LFINTOSC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor is enabled.
FIGURE 3-1:
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
FIGURE 3-2:
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q4
Q3
Q2
OSC1
Peripheral
Program
Q1
SOSCI
Q1
Counter
Clock
CPU
Clock
PC + 2
PC
123
n-1
n
Clock Transition(1)
Q4
Q3
Q2
Q1
Q3
Q2
PC + 4
Note 1: Clock transition typically occurs within 2-4 TOSC.
Q1
Q3 Q4
OSC1
Peripheral
Program
PC
SOSC
PLL Clock
Q1
PC + 4
Q2
Output
Q3
Q4
Q1
CPU Clock
PC + 2
Clock
Counter
Q2
Q3
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
SCS<1:0> bits Changed
TPLL(1)
12
n-1
n
Clock
OSTS bit Set
Transition(2)
TOST(1)
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